Posted by Big Gav in energy efficiency
Technology Review has an article on a new low power technology for portable devices - Low-Cost Tablet Runs on Three Watts of Power.
After a year of testing in a remote village in India, researchers are ready to scale up production of an ultra-low-power $35 tablet called the I-slate.
The I-slate is designed to teach math and other subjects to students whose schools lack electricity or to students who don't have access to teachers at all. The device will enter full-scale production next year, and will be the first device to apply a low-power technology called probabilistic CMOS (complementary metal-oxide semiconductor) to achieve a longer battery life.
The probabilistic CMOS approach is simple: run an ordinary microchip less stringently, sacrifice a small amount of precision, and get huge gains in energy efficiency in return. Probabilistic CMOS (CMOS refers to the technology behind most of today's chip technologies) works particularly well in graphics and sound processing, since human vision and hearing aren't perfect, and small errors are therefore undetectable.
Krishna Palem, a professor at Rice University and director of the Institute for Sustainable Nanoelectronics at Nanyang Technological University, first demonstrated probabilistic CMOS in 2006. Palem is now working on getting the technology into applications including a low-power hearing aid. In the educational tablet device, Palem says, probabilistic chips will enable huge power savings: the educational tablet will require just three watts of power, meaning it can be powered entirely by small solar cells like those on a pocket calculator.